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  4. Sirocco: cost-effective fine-grain distributed shared memory
 
conference paper

Sirocco: cost-effective fine-grain distributed shared memory

Schoinas, Ioannis
•
Falsafi, Babak  
•
Hill, Mark D.
Show more
1998
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques

Software fine-grain distributed shared memory (FGDSM) provides a simplified shared-memory programming interface with minimal or no hardware support. Originally software FGDSMs targeted uniprocessor-node parallel machines. This paper presents Sirocco, a family of software FGDSMs implemented on a network of low-cost SMPs. Sirocco takes full advantage of SMP nodes by implementing inter-node sharing directly in hardware and overlapping computation with protocol execution. To maintain correct shared-memory semantics, however SMP nodes require mechanisms to guarantee atomic coherence operations. Multiple SMP processors may also result in contention for shared resources and reduce performance. SMP nodes also impact the cost trade-off. While SMPs typically charge higher price-premiums, for a given system size SMP nodes substantially reduce networking hardware requirement as compared to uniprocessor nodes. In this paper, we ask the question “Are SMPs cost-effective building blocks for software FGDSM?” We present experimental measurements on Sirocco implementations ranging from an all-software system to a system with minimal hardware support. Together with simple cost models we show that low-cost SMP nodes: (i) result in competitive performance with uniprocessor nodes, (ii) substantially reduce hardware requirement and are more cost- effective than uniprocessor nodes, (iii) significantly benefit from hardware support for coherence operations, and (iv) are especially beneficial for FGDSMs with high-overhead coherence operations

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Type
conference paper
DOI
10.1109/PACT.1998.727144
Author(s)
Schoinas, Ioannis
Falsafi, Babak  
Hill, Mark D.
Larus, James R.
Wood, David A.
Date Issued

1998

Published in
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques
Start page

40

End page

49

Editorial or Peer reviewed

REVIEWED

Written at

OTHER

EPFL units
PARSA  
VLSC  
Event placeEvent date
Available on Infoscience
April 6, 2009
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/36911
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