Repository logo

Infoscience

  • English
  • French
Log In
Logo EPFL, École polytechnique fédérale de Lausanne

Infoscience

  • English
  • French
Log In
  1. Home
  2. Academic and Research Output
  3. Journal articles
  4. Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design
 
research article

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Kazi, Ibrahim
•
Meinerzhagen, Pascal
•
Gaillardon, Pierre-Emmanuel
Show more
2014
IEEE Transactions on Circuits and Systems Part 1 Regular Papers

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT) or even to the subthreshold (sub-VT) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present and compare ReRAM-based Non-Volatile Flip-Flop (NVFF) topologies which are optimized for low-voltage operation (including near-VT and sub-VT operation). Three low-voltage NVFF circuit topologies are proposed and evaluated in terms of energy dissipation and reliability. Using topologies with two complementary programmed ReRAM devices, Monte Carlo simulations accounting for parametric variations confirm reliable data restore operation from the ReRAM devices at a sub- voltage as low as 400 mV. A topology using a single ReRAM device exhibits lower write energy, but requires a near- voltage for robust read. Energy characterization is performed at nominal, near-VT , and sub-VT supply voltages. The minimum energy point is reached for near-VT read operation with a total read+write energy of 735 fJ.

  • Files
  • Details
  • Metrics
Type
research article
DOI
10.1109/TCSI.2014.2334891
Web of Science ID

WOS:000344467500011

Author(s)
Kazi, Ibrahim
Meinerzhagen, Pascal
Gaillardon, Pierre-Emmanuel
Sacchetto, Davide  
Leblebici, Yusuf  
Burg, Andreas  
De Micheli, Giovanni  
Date Issued

2014

Publisher

Institute of Electrical and Electronics Engineers

Published in
IEEE Transactions on Circuits and Systems Part 1 Regular Papers
Volume

61

Issue

11

Start page

3155

End page

3164

Subjects

Flip-flops

•

low-power electronics

•

nonvolatile memory

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
TCL  
LSM  
LSI1  
Available on Infoscience
September 30, 2014
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/107131
Logo EPFL, École polytechnique fédérale de Lausanne
  • Contact
  • infoscience@epfl.ch

  • Follow us on Facebook
  • Follow us on Instagram
  • Follow us on LinkedIn
  • Follow us on X
  • Follow us on Youtube
AccessibilityLegal noticePrivacy policyCookie settingsEnd User AgreementGet helpFeedback

Infoscience is a service managed and provided by the Library and IT Services of EPFL. © EPFL, tous droits réservés