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  4. Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity
 
research article

Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

De Marchi, Michele  
•
Sacchetto, Davide  
•
Zhang, Jian  
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2014
IEEE Transactions on Nanotechnology

Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the fabrication of novel ambipolar Silicon nanowire (SiNW) Schottky-barrier (SB) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. A top-down approach was employed for the nanowire fabrication, using an e-beam lithography defined design pattern. In these transistors, one gate electrode enables the dynamic configuration of the device polarity (n- or p-type) by electrostatic doping of the channel in proximity of the source and drain SBs. The other gate electrode, acting on the center region of the channel switches ON or OFF the device. Measurement results on silicon show I-on/I-off > 10(6) and subthreshold slopes approaching the thermal limit, SS approximate to 64 mV/dec (70 mV/dec) for p(n)-type operation in the same physical device. Finally, we show that the XOR logic operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional two-transistor XOR gate.

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Type
research article
DOI
10.1109/Tnano.2014.2363386
Web of Science ID

WOS:000345087900003

Author(s)
De Marchi, Michele  
Sacchetto, Davide  
Zhang, Jian  
Frache, Stefano
Gaillardon, Pierre-Emmanuel
Leblebici, Yusuf  
De Micheli, Giovanni  
Date Issued

2014

Publisher

Institute of Electrical and Electronics Engineers

Published in
IEEE Transactions on Nanotechnology
Volume

13

Issue

6

Start page

1029

End page

1038

Subjects

Ambipolar transistor

•

Bosch process

•

double-gate

•

dual-gate

•

e-beam lithography

•

gate-all-around (GAA)

•

polarity control

•

silicon nanowire (SiNW)

•

top-down fabrication

•

XOR logic gate

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

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Available on Infoscience
October 3, 2014
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/107227
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