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  4. Leveraging Parallel Nesting in Transactional Memory
 
conference paper

Leveraging Parallel Nesting in Transactional Memory

Baretto, Joao
•
Dragojevic, Aleksandar  
•
Ferreira, Paulo
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2010
Proceedings of the 15th ACM SIGPLAN symposium on Principles and Practice of Parallel Computing
15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

Exploiting the emerging reality of affordable multi-core architectures goes through providing programmers with simple abstractions that would enable them to easily turn their sequential programs into concurrent ones that expose as much parallelism as possible. While transactional memory promises to make concurrent programming easy to a wide programmer community, current implementations either disallow nested transactions to run in parallel or do not scale to arbitrary parallel nesting depths. This is an important obstacle to the central goal of transactional memory, as programmers can only start parallel threads in restricted parts of their code. This paper addresses the intrinsic difficulty behind the support for parallel nesting in transactional memory, and proposes a novel solution that, to the best of our knowledge, is the first practical solution to meet the lowest theoretical upper bound known for the problem. Using a synthetic workload configured to test parallel transactions on a multi-core machine, a practical implementation of our algorithm yields substantial speed-ups (up to 22x with 33 threads) relatively to serial nesting, and shows that the time to start and commit transactions, as well as to detect conflicts, is independent of nesting depth.

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Type
conference paper
DOI
10.1145/1693453.1693466
Web of Science ID

WOS:000280548100009

Author(s)
Baretto, Joao
Dragojevic, Aleksandar  
Ferreira, Paulo
Guerraoui, Rachid  
Kapalka, Michal
Date Issued

2010

Publisher

ACM

Published in
Proceedings of the 15th ACM SIGPLAN symposium on Principles and Practice of Parallel Computing
Start page

91

End page

100

Subjects

Nested parallel programs

•

Fork-join

•

Work-stealing

•

Transactional memory

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
DCL  
Event nameEvent placeEvent date
15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

Bangalore, India

January 9-14, 2010

Available on Infoscience
February 2, 2010
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/46355
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