Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed variability of the RF proposing different compile-time and run-time design alternatives. The first alternative extends current RF architectures and uses a compile-time variability-aware register assignment algorithm. The second alternative presents a fully-adjustable pure run-time approach, which overcomes the variability loss as well, but at the extra cost of cycles and area. However, the savings achieved and the run-time management of the register delay variations without any support from the user, show a very promising application field. Our results in embedded system benchmarks show that variability can be tackled without significant performance penalty, and trade-offs between performance and area are possible thanks to the whole design spectrum provided by the two presented alternatives.

Published in:
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, USA, 121-124
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana, USA, May 27-30, 2007

 Record created 2007-01-24, last modified 2019-03-16

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