NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. We also present an automated way to perform NoC features exploration using the interaction HW/SW on an FPGA. Our experimental results show a speed-up of four orders of magnitude with respect to cycleaccurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.

Published in:
Proceedings of the International Conference on Parallel Computing (ParCo 2005), 753-760
Presented at:
International Conference on Parallel Computing (ParCo2005), Malaga, Spain, September 13-16, 2005

 Record created 2006-11-01, last modified 2018-03-18

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