Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can lead to deadlock-free operation with minimum power and area overhead are important for designing application-specific NoCs. A major class of deadlocks that occur in NoCs are due to the dependencies among the resources shared by different message types. In this work, we consider the problem of avoiding message-dependent deadlocks during the NoC topology synthesis phase. We show that by considering this issue during topology synthesis, we can obtain a significantly better NoC design than traditional methods, where the deadlock avoidance issue is dealt with separately. Our experiments on several SoC benchmarks show that our proposed scheme provides large reduction in NoC power consumption (an average of 38.5%) and NoC area (an average of 30.7%) when compared to traditional approaches.

Published in:
Proceedings of IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), 158-163
Presented at:
IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), Nice, France, October 16-18, 2006

 Record created 2006-09-07, last modified 2018-03-18

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