Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are designed. Measurement results of the manufactured design show operation at data rates exceeding 2.5-Gbps/channel for the detector, the amplification and the clock and data recovery circuits. This proof of concept is the first step towards design optimized, completely integrated, multi-channel optical receivers for high-bandwidth short-distance chip-to-chip interconnects.


Published in:
proceedings of the 32nd European Solid-State Circuits Conference (ESSCIRC), 480-483
Presented at:
32nd European Solid-State Circuits Conference (ESSCIRC), Montreux, Switzerland, September 18-22
Year:
2006
Publisher:
IEEE
Keywords:
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 Record created 2006-07-12, last modified 2018-03-17

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