Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links
This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are designed. Measurement results of the manufactured design show operation at data rates exceeding 2.5-Gbps/channel for the detector, the amplification and the clock and data recovery circuits. This proof of concept is the first step towards design optimized, completely integrated, multi-channel optical receivers for high-bandwidth short-distance chip-to-chip interconnects.
- URL: http://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=4099808&isnumber=4099685&punumber=4099684&k2dockey=4099808@ieeecnfs&query=%28%28tajalli+a.%29%3Cin%3Eau+%29&pos=21&access=no
Record created on 2006-07-12, modified on 2016-08-08