A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output (I/O) interfaces is subject to much slower growth, due to the limited number of packaging pins and the intrinsic bandwidth constraint of electrical parallel buses. While upcoming serial interfaces provide some relief to this problem in the short term, their data rates remain subject to the inherent bandwidth-distance trade-off in electrical data links. A major move to an optical data link paradigm for very short-distance (board-to-board and chip-to-chip) communications would allow for considerable I/O interface bandwidth enhancement, but this solution currently lacks economic success. Today's optical receivers indeed use compound semiconductor photodetectors in combination with bipolar or BiCMOS amplifiers and CMOS clock and data recovery circuits. The move to fully integrated silicon CMOS receivers would contribute to cost reduction in several ways. Monolithic integration is not only mandatory for optical receivers to become a true I/O interface, it also results in lower volume manufacturing cost, improved yield and reduced assembly and test expenses. The presented work deals with the general problem of monolithic integration and shows the feasibility of fully integrated multi-channel CMOS-compatible fiber-optic receivers for short-distance communications. Multiple challenges, related to the limitations of high-performance analog design in advanced CMOS processes, as well as the combination with a novel silicon photodetector, are addressed. An important realization in this context is that complete integration of the receiver allows for a system-level (global) optimization approach of all components. In this context, we introduce a top-down design methodology propagating the system-level receiver specifications down to the block level, then to the transistor-level. Based on these specifications, transimpedance and limiting amplifier designs are proposed. The limiting amplifier in particular has been designed according to a scaling method for area and power optimization. Magnetic inter-channel coupling effects in multi-channel receivers with inductive peaking have been analyzed, both in theory and by measurement. The clock and data recovery circuit is based on a compact gated oscillator topology and achieves low power and area through partial resource sharing. As this particular topology is not conventionally used for such applications, a novel modeling and verification approach based on statistical and behavioral simulation is proposed. This methodology allows to determine the required power consumption for given jitter specifications and thus results in a power-optimized design. A low-power low-area gated-oscillator clock recovery circuit has been implemented to verify the presented methodology. In summary, a global top-down approach to the design of fiber-optic receivers is presented. Operation of all building blocks at or above the targeted per channel data rate of 2.5Gb/s shows the feasibility of monolithically integrated multi-channel optical receivers in standard CMOS technologies.

Leblebici, Yusuf
Lausanne, EPFL
Other identifiers:
urn: urn:nbn:ch:bel-epfl-thesis3600-5

Note: The status of this file is: EPFL only

 Record created 2006-06-13, last modified 2018-01-27

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