A tool named SPARCS‐A for compaction of integrated circuits with analogue constraints is presented. the approach is structured in two steps. First a robust and efficient constraint graph compaction algorithm produces a compacted layout quickly, where parasitics are controlled so as to guarantee that the performance constraints are met. Next the layout produced by the first step is fed into a linear programming (LP) solver which enforces symmetries and performs global interconnect length minimization. the computational cost of the iterative LP solver is modest, because its initial state is the configuration found by the constraint graph algorithm and only symmetry constraints need to be enforced. With considerable computational efficiency this algorithm produces a compacted layout which satisfies the high‐level performance constraints and is feasible for practical use within industrial‐strength analogue synthesis systems. the use of such a compactor allows one to relax the requirements on parasitic control during placement and routing, thus improving the efficiency of the entire layout design process.