MONOLITHIC INTEGRATION OF NANOMECHANICAL RESONATORS WITH CMOS CIRCUITRY: FULL-WAFER NANOPATTERNING BY NANOSTENCIL LITHOGRAPHY
For the purpose of integrating nanomechanical structures with CMOS circuitry, nanostencil lithography ensures parallel patterning for rapid processing at wafer scale and nanometer-sized features definition. Moreover, this patterning technique is compatible with CMOS substrates given that it does not alter circuitry performance. However, a major limitation in nanostencil lithography is gap-induced pattern blurring naturally occurring if a planar stencil is used in combination with a substrate containing topography (e.g. CMOS). This phenomenon has been characterized and a corrective technique is implemented in order to eliminate the blurring.
Arcamone_Julien_CMI_2006.pdf
restricted
1.28 MB
Adobe PDF
d5d6724ac748f1f2913979d06ea5b23c