Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot
Roggen, D.; Hofmann, S.; Thoma, Y.; Floreano, D.
2003

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Abstract

A cellular hardware implementation of a spiking neural network with run-time reconfigurable connectivity is presented. It is implemented on a compact custom FPGA board which provides a powerful reconfigurable hardware platform for hardware and software design. Complementing the system, a CPU synthesized on the FPGA takes care of interfacing the network with the external world. The FPGA board and the hardware network are demonstrated in the form of a controller embedded on the Khepera robot for a task of obstacle avoidance. Finally, future implementations on new multi-cellular hardware are discussed.

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Title Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot
Author(s) Roggen, D. ; Hofmann, S. ; Thoma, Y. ; Floreano, D.
Published in NASA/DoD Conference on Evolvable Hardware (EH'2003)
Pages 189-198
Conference NASA/DoD Conference on Evolvable Hardware (EH'2003), Chicago, Illinois, USA, July 9-11
Date 2003
Keywords
Note Lohn, J. and Zebulum, R. and Steincamp, J. and Keymeulen, D. and Stoica, A. and Ferguson, M. I. (eds.)
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LSL
Record Appears in Scientific production and competences > Archives > I&C - School of Computer and Communication Sciences > LSL - Logic Systems Laboratory
Scientific production and competences > STI - School of Engineering > IMT - Institute of Microengineering > LIS - Laboratory of Intelligent Systems
Peer-reviewed publications
Conference Papers
Work produced at EPFL
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