A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18µm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/Ch and each channel occupies 0.045µm2 silicon area.


Published in:
Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC), 193-196
Presented at:
31st European Solid-State Circuits Conference ESSCIRC, Grenoble, France, September 12-16
Year:
2005
Keywords:
Laboratories:




 Record created 2005-12-06, last modified 2018-03-17

n/a:
Download fulltextPDF
External link:
Download fulltextURL
Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)