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research article
Design, Synthesis, and Test of Network on Chips
For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.
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Name
Pande_Design Synthesis_10.pdf
Access type
openaccess
Size
145.99 KB
Format
Adobe PDF
Checksum (MD5)
2515e2701625e3c586043f45d191e99f