Optimization of Reliability and Power Consumption in Systems on a Chip

Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature, have made reliability assessment a much more significant issue in design. Although reliability of devices and interconnect has been broadly studied, here we characterize reliability at the system level. Thus we consider component-based System on Chip designs. Reliability is strongly affected by system temperature, which is in turn driven by power consumption. Thus, component reliability and their power management should be addressed jointly. We present here a joint reliability and power management optimization problem whose solution is an optimal management policy. When careful joint policy optimization is performed, we obtain a significant improvement in energy consumption (40%) in tandem with meeting reliability constraint for all operating temperatures.


Published in:
Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 237-246
Presented at:
International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Leuven, Belgium, September 21-23, 2005
Year:
2005
Laboratories:




 Record created 2005-09-22, last modified 2018-01-27

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