A Novel Approach for Network on Chip Emulation

Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a range of solutions, as well as characterize quickly performance figures.

Published in:
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2365-2368
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, May 23-26, 2005

 Record created 2005-09-14, last modified 2018-03-18

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