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conference paper
Design and Realization of a 2.4 Gbps - 3.2 Gbps Clock and Data Recovery Circuit Using Deep-Submicron Digital CMOS Technology
2003
IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings
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Name
CDR_soc-03_edited.pdf
Access type
openaccess
Size
232.51 KB
Format
Adobe PDF
Checksum (MD5)
68809e0be8cdc1fc1644ea26fc71bf68