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conference paper
A highly fault tolerant PLA architecture for failure-prone nanometer CMOS and novel quantum device technologies
2004
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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Name
dft04.pdf
Access type
openaccess
Size
855.62 KB
Format
Adobe PDF
Checksum (MD5)
9b46d8bd6c172530e63283ebafe76852