Self-Calibrating Networks-On-Chip

Networks-on-chip provide an elegant framework to efficiently reuse predesigned cores. However, reuse of cores is jeopardized by new deep sub-micron noise effects that challenge the reliability of CMOS technology. Moreover, noise margins are further reduced as supply voltages scale down. We advocate that self-calibrating techniques will be needed to maintain an acceptable design trade-off between energy, performance, and reliability. As a result, self-calibrating techniques have to be integrated within networks-on-chip. This paper presents a self-calibrating link and discusses qualitatively the problem of controlling adaptively its voltage and frequency.


Published in:
Proceedings of the IEEE International Symposium on Circuits and Systems, 3, 2361-2364
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 23-26, 2005
Year:
2005
ISBN:
0-7803-8834-8
Keywords:
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 Record created 2005-08-08, last modified 2018-05-01

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