A Complete Network-On-Chip Emulation Framework

Current systems-on-chip (SoC) execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoC can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.


Published in:
Proceedings of the Design, Automation and Test in Europe Conference (DATE), 1, 246 - 251
Presented at:
Design, Automation and Test in Europe Conference (DATE), Munich, Germany, March 7-11, 2005
Year:
2005
Laboratories:




 Record created 2005-07-29, last modified 2018-01-27

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