A discrete Fourier-cosine transform chip

An 8-point Fourier-cosine transform chip designed for a data rate of 100 Mbits/s is described. The top-down design is presented step by step, including algorithm modification for VLSI suitability, architectural choices, testing overhead, internal precision assignments, mask generation, and finally, verification of the layout. A high-level language (C) design tool was developed concurrently with the layout. This tool allows mimicking exactly the different representations of the algorithm: software, mask, and chip. This provides an automatic cross-checking at all design stages. The VLSI environment created by this tool, as well as existing powerful CAD tools, made a fast design-time possible.


Published in:
IEEE Journal on Selected Areas in Communications, 4, 1, 49-61
Year:
1986
Laboratories:




 Record created 2005-04-18, last modified 2018-05-01

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