Contribution to the development of the acquisition electronics for the LHCb experiment

The LHCb experiment is one of the four large particle detectors currently under construction at the LHC accelerator at CERN. It is a forward single-arm spectrometer dedicated to precision measurements of CP violation and rare decays in the b quark sector. In the Standard Model CP violation arises via the complex phase of the 3x3 CKM quark mixing matrix. The LHCb experiment will test the unitarity of this matrix by measuring in several theoretically unrelated ways all angles and all sides of the unitarity triangle. This will allow to over-constrain the model and — hopefully — to exhibit inconsistencies which will be a signal of physics beyond the Standard Model. The LHCb detector consists of roughly 10 million sensors and is read out every LHC bunch crossing at 40 MHz. In the subsequent selection of events a multilevel trigger scheme is applied. The data is required to reside in the radiation environment on the front-end chips until the first level trigger (L0) decision is taken. For the second level trigger (L1) processing, the data is transmitted over long analog copper or digital optical links to the data acquisition board called TELL1 (Trigger ELectronics Level 1 board). TELL1 is now used by essentially all sub-detectors of LHCb. It provides the interface to the copper and optical link systems and performs intensive processing. This includes event synchronization, link compensation for the analog readout, pedestal calculation and subtraction, common mode suppression, zero suppression, L1 buffering, multi event packaging, and encapsulation into IP compliant Ethernet packets. The output of the board is sent to the Gigabit based event builder network and processed on the the combined L1 and High Level Trigger CPU farm. The data rate of 30 Gbit/s on the input of TELL1 can be managed using large FPGAs, highest density DDR SDRAM and fast PCB interconnects. In this document a proposal for the processing steps is given, the Level 1 buffer implementation is discussed, and design consideration concerning signal integrity are made.


Advisor(s):
Bay, Aurélio
Year:
2004
Publisher:
Lausanne, EPFL
Other identifiers:
urn: urn:nbn:ch:bel-epfl-thesis3054-4
Laboratories:


Note: The status of this file is: EPFL only


 Record created 2005-03-16, last modified 2018-05-01

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