Fully integrated Si:HfO2 Negative Capacitance 2D-2D WSe2/SnSe2 Subthermionic Tunnel FETs
We report the first experimental demonstration and performance characterization of a fully integrated negative capacitance (NC) WSe2/SnSe2 p-type Tunnel FETs (TFETs), validating the use of NC as a technology booster to achieve a significantly improved sub-thermionic electronic switch. A WSe2/SnSe2 TFET with sub-60 mV/dec subthreshold slope (SS) is employed as the baseline TFET and characterized by using internal metal as a gate. The universal boosting impact of an NC effect of silicon-doped HfO2 on digital and analog performances of 2D/2D TFETs is reported. A sub-30 mV/dec point SS and 50 mV/dec average swing over 2.5 decades of current with I-on/I-off > 10(4) at V-D = 500 mV are reported. Moreover, the low-slope region and I-60 figures of merit are extended by 1.5 orders of magnitude due to the internal voltage amplification of the NC. The NC area of the polarization characteristic of Si:HfO2 is extracted for all the investigated drain voltages based on the experimental data measured in DC mode. Importantly, the supply voltage is reduced by 0.3 V by NC to achieve the same output current, I-on. Our results fully demonstrate the combined merits of band-to-band-tunneling in 2D/2D WSe2/SnSe2 heterostructure with NC as a universal performance booster for 2D Tunnel FETs, offering to future 2D platforms a path towards improved energy efficiency.
WOS:000886608500036
2022-01-01
978-1-6654-8494-7
New York
161
164
REVIEWED
Event name | Event place | Event date |
Milan, ITALY | Sep 19-22, 2022 | |