Repository logo

Infoscience

  • English
  • French
Log In
Logo EPFL, École polytechnique fédérale de Lausanne

Infoscience

  • English
  • French
Log In
  1. Home
  2. Academic and Research Output
  3. Journal articles
  4. Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis
 
research article

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Bloch, Aurelien  
•
Casale-Brunet, Simone  
•
Mattavelli, Marco  
September 1, 2022
Journal Of Low Power Electronics And Applications

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental components and features of both the design and of the platform to maximize the overall performance. The dataflow programming approach has proven to be an appropriate methodology for reaching such a difficult and complex goal for the intrinsic portability and the possibility of easily decomposing a network of actors on different processing units of the heterogeneous hardware. Nonetheless, such a design method might not be enough on its own to achieve the desired performance goals, and supporting tools are useful to be able to efficiently explore the design space so as to optimize the desired performance objectives. This article presents a methodology composed of several stages for enhancing the performance of dataflow software developed in RVC-CAL and generating low-level implementations to be executed on GPU/CPU heterogeneous hardware platforms. The stages are composed of a method for the efficient scheduling of parallel CUDA partitions, an optimization of the performance of the data transmission tasks across computing kernels, and the exploitation of dynamic programming for introducing SIMD-capable graphics processing unit systems. The methodology is validated on both the quantitative and qualitative side by means of dataflow software application examples running on platforms according to various different mapping configurations.

  • Details
  • Metrics
Type
research article
DOI
10.3390/jlpea12030040
Web of Science ID

WOS:000858554200001

Author(s)
Bloch, Aurelien  
Casale-Brunet, Simone  
Mattavelli, Marco  
Date Issued

2022-09-01

Publisher

MDPI

Published in
Journal Of Low Power Electronics And Applications
Volume

12

Issue

3

Start page

40

Subjects

Engineering, Electrical & Electronic

•

Engineering

•

heterogeneous systems

•

gpu programming

•

source-to-source compiler

•

parallel computing

•

simd

•

rvc-cal

•

dynamic dataflow programs

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
SCI-STI-MM  
Available on Infoscience
October 10, 2022
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/191307
Logo EPFL, École polytechnique fédérale de Lausanne
  • Contact
  • infoscience@epfl.ch

  • Follow us on Facebook
  • Follow us on Instagram
  • Follow us on LinkedIn
  • Follow us on X
  • Follow us on Youtube
AccessibilityLegal noticePrivacy policyCookie settingsEnd User AgreementGet helpFeedback

Infoscience is a service managed and provided by the Library and IT Services of EPFL. © EPFL, tous droits réservés