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  4. Negative Capacitance in HfO2 Gate Stack Structures With and Without Metal Interlayer
 
research article

Negative Capacitance in HfO2 Gate Stack Structures With and Without Metal Interlayer

Gastaldi, Carlotta  
•
Cavalieri, Matteo  
•
Saeidi, Ali  
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March 25, 2022
Ieee Transactions On Electron Devices

In this work, we experimentally explore and compare FET gate stacks with and without an inner metal plane between a linear dielectric (SiO2) and a ferroelectric layer (Si-doped HfO2) operating in the negative capacitance (NC) regime. The use of nanosecond-range pulses enables us to observe hysteresis-free NC and reconstruct the S-shaped polarization-voltage curves. The devices with the inner metal plate show a higher equivalent NC value, which offers the potential for a higher differential amplification in a NC-FET. However, such a NC region is observed over a smaller range of electric field and polarization, which leads to hysteresis. Moreover, the presence of a metal layer in between the ferroelectric and the insulator favors domain formation resulting in destabilization of the NC effect. For the gate structure where the ferroelectric and the insulator are in contact, the S-shaped polarization-voltage curve shows a better agreement with Landau-Ginzburg-Devonshire formalism for the monodomain state. The uniform polarization closely mimicking the monodomain state is possible due to the polarization imprint occurring due to the structural asymmetry. By nanometer resolution polarization mapping via off-resonance piezoelectric force microscopy (PFM), we corroborate the presence of imprint, which can intrinsically stabilize one ferroelectric state. Overall, the article provides an experimental demonstration that the absence of the inner metal plane in the gate structures stabilizes the NC regime favorable for hysteresis-free NC-FET.

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Type
research article
DOI
10.1109/TED.2022.3157579
Web of Science ID

WOS:000777133500001

Author(s)
Gastaldi, Carlotta  
•
Cavalieri, Matteo  
•
Saeidi, Ali  
•
O'Connor, Eamon  
•
Bellando, Francesco  
•
Stolichnov, Igor  
•
Ionescu, Adrian M.  
Date Issued

2022-03-25

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Published in
Ieee Transactions On Electron Devices
Volume

69

Issue

5

Start page

2680

End page

2685

Subjects

Engineering, Electrical & Electronic

•

Physics, Applied

•

Engineering

•

Physics

•

logic gates

•

metals

•

capacitance

•

voltage measurement

•

hysteresis

•

electrodes

•

semiconductor device measurement

•

ferroelectric materials

•

gate stack

•

hafnium oxide

•

negative capacitance (nc)

•

nc-fet

•

behavior

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

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Available on Infoscience
April 25, 2022
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/187262
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