An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks
We propose an ultra-low-power (ULP) image signal processor (ISP) that performs on-the-fly in-processing frame compression/decompression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence. This approach reduces energy consumption spent processing and transmitting unimportant image data to achieve a 16 × imaging system energy gain in an intruder detection scenario. The ISP was fabricated in 40-nm CMOS and consumes only 170 μW at 5 frames/s for neural network-based intruder detection and 192 × compressed image recording.
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An, H., Schiferl, S., Venkatesan, S., Wesley, T., Zhang, Q., Wang, J., Choo, K. D., Liu, S., Liu, B., Li, Z., Gong, L., Zhong, H., Blaauw, D., Dreslinski, R., Kim, H. S., & Sylvester, D. (2020). An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks. IEEE Journal of Solid-State Circuits, 56(4), 1071–1081. https://doi.org/10.1109/JSSC.2020.3041858
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2020
56
4
1071
1081
REVIEWED
OTHER