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conference paper
A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge
2020
2020 IEEE Symposium on VLSI Circuits proceedings
We propose an ultra-low power (ULP) Image Signal Processor (ISP) that performs on-the-fly in-processing frame (de)compression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence to achieve a 16× imaging system energy gain. The ISP is fabricated in 40 nm CMOS and consumes only 170 μW at 5 fps for neural network-based intruder detection and 192× compressed image recording.
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Type
conference paper
Authors
An, Hyochan
•
Venkatesan, Siddharth
•
Schiferl, Sam
•
Wesley, Tim
•
Zhang, Qirui
•
Wang, Jingcheng
•
•
Liu, Shiyu
•
Liu, Bowen
•
Li, Ziyun
Publication date
2020
Publisher
Published in
2020 IEEE Symposium on VLSI Circuits proceedings
Start page
1
End page
2
Peer reviewed
REVIEWED
EPFL units
Event name | Event place | Event date |
Honolulu, HI, USA | 16-19 June 2020 | |
Available on Infoscience
April 1, 2022