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conference paper
A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference
2017
2017 IEEE Custom Integrated Circuits Conference proceedings
This work presents a start-up boosting circuit designed for fast stabilization of a 2-transistor voltage reference. A clock injection method is used to induce a large bias on the 2-transistor voltage reference resulting in a fast output voltage settling which is critical to reducing initialization time for analog components, reducing energy consumption. The fast stabilization technique is implemented in 180nm CMOS process and uses 0.404mm 2 of area. Measurement from test chips shows 50.4μW power consumption during start-up phase with 133x speed gain.
Type
conference paper
Authors
Publication date
2017
Publisher
Published in
2017 IEEE Custom Integrated Circuits Conference proceedings
Start page
1
End page
4
Peer reviewed
REVIEWED
EPFL units
Event name | Event place | Event date |
Austin, TX, USA | 30 April-3 May 2017 | |
Available on Infoscience
April 1, 2022
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