To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is that these ADCs are large and therefore suffer from interleaving artifacts related to size [1]. Compact, efficient SAR ADCs are needed to address this problem. As an alternative, multiple-bit-per-cycle SAR ADCs deliver high speed from a single SAR ADC, but at the cost of significant added complexity (i.e., extra quantizers and capacitor DACs) and die area [2,3]. This work addresses the need for a fast, compact SAR ADC, with a 1GS/s SAR ADC that has the best Walden FOM and the smallest area among 5-to-6.3b ADCs published in ISSCC (see Fig. 27.3.1).