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  4. Turning PathFinder Upside -Down: 1-4,xploring FPGA Switch -Blocks by Negotiating Switch Presence
 
conference paper

Turning PathFinder Upside -Down: 1-4,xploring FPGA Switch -Blocks by Negotiating Switch Presence

Nikolic, Stefan  
•
Ienne, Paolo  
January 1, 2021
2021 31St International Conference On Field-Programmable Logic And Applications (Fpl 2021)
31st International Conference on Field-Programmable Logic and Applications (FPL)

Automated switch-block exploration gains in importance as technology scaling brings more emphasis on the physical constraints, making it insufficient to rely on abstract measures of routability alone. In this work, we take an approach that significantly differs from the previously used ones, relying mostly on general optimization methods: we essentially let the router itself design the switch -pattern. Of course, letting the router make arbitrary choices would be rather ineffective, as there would be nothing to prevent it from spreading routes over many different switches, making it difficult to understand if a particular one was used because it is essential for proper implementation of a given circuit, or simply due to some local, largely irrelevant decision. Instead, we change the method of node pricing in a negotiated congestion router, by applying the same principles in the opposite direction, to make it reach a consensus on switches that are worthy of being included in the final switch -pattern. With this, we obtained a pattern that outperforms the one reached through simulated annealing optimization by 10.7% in terms of average routed critical path delay and uses less than half the number of switches, without compromising routability.

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Type
conference paper
DOI
10.1109/EPL53798.2021.00044
Web of Science ID

WOS:000728589800035

Author(s)
Nikolic, Stefan  
Ienne, Paolo  
Date Issued

2021-01-01

Publisher

IEEE COMPUTER SOC

Publisher place

Los Alamitos

Published in
2021 31St International Conference On Field-Programmable Logic And Applications (Fpl 2021)
ISBN of the book

978-1-6654-3759-2

Series title/Series vol.

International Conference on Field Programmable Logic and Applications

Start page

225

End page

233

Subjects

Computer Science, Hardware & Architecture

•

Computer Science, Software Engineering

•

Computer Science, Theory & Methods

•

Engineering, Electrical & Electronic

•

Computer Science

•

Engineering

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LAP  
Event nameEvent placeEvent date
31st International Conference on Field-Programmable Logic and Applications (FPL)

ELECTR NETWORK

Aug 30-Sep 03, 2021

Available on Infoscience
January 15, 2022
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/184470
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