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patent
Memory chip or memory array for wide-voltage range in-memory computing using bitline technology
2021
A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines.
Type
patent
EPO Family ID
77274023
TTO classification
TTO:6.2092.1
TTO:6.2092.2
Patent number | Country code | Kind code | Date issued |
US11094355 | US | B1 | 2021-08-17 |
Available on Infoscience
September 1, 2021
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