The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These two requirements introduce new challenges, such as higher bandwidth and higher integration, in terms of data transfer and processing of trigger systems. Both problems have to be addressed, ensuring that hardware and firmware have low and fixed latency, and are reliable. Low latency is essential due to the limited storage available in the detector front-end pipelined memories. Fixed latency is needed because the trigger processing is pipelined, and the inputs need to be time-aligned at every processing step. Reliability is important for high trigger efficiency. If the trigger is not reliable, rare events can be discarded, and uninteresting events accepted. This Ph.D. thesis presents the upgrade of part of the trigger system of ATLAS (A Toroidal LHC AparatuS). ATLAS is one of the detectors at the world's largest and most powerful particle collider, the LHC (Large Hadron Collider) at CERN (European Center of Nuclear Research). The online trigger system of ATLAS is segmented in two levels. The first level is implemented with custom electronics. For the parts of the first level trigger not exposed to radiation, digital processing is primarily implemented using FPGA (Field Programmable Gate Array) devices. FPGAs offer high processing capacity with low-latency and re-programmability, i.e., the capability of changing the implemented logic. The second level is built from commercial computers, network switches, and custom software. The rate of bunch of particles crossing in the interaction point is 40 MHz, and the first level (Level-1) trigger needs to reduce the rate down to 100 kHz with a very low latency of 2.5 us. Part of the Level-1 trigger system, the MUCTPI (Muon to Central Trigger Processor Interface) connects the output of the barrel and endcap muon trigger to the CTP (Central Trigger Processor), which takes the final Level-1 accept decision. The first part of this Ph.D. thesis addresses the work on the data transfer part of the MUCTPI. Latency optimized FPGA (Field Programmable Gate Array) MGT (Multi-Gigabit Transceiver) configurations have been found. Moreover, an IP (Intellectual Property) core to synchronize data from 208 SL inputs with low and fixed latency has been developed. The total data transfer and synchronization latency is below 125 ns, corresponding to 60% of the latency budget. All MUCTPI on-board and off-board high-speed serial links have been tested. The Bit Error Rate (BER) values for all links running at 12.8 Gb/s have been measured as lower than one bit error per day with a confidence level of 95%. This value is acceptable as it corresponds to only one potential fake trigger or lost event per day. The second part of this thesis covers the development of the MUCTPI sorting network and its FPGA implementation using RTL (Register-Transfer Level) and HLS (High-Level Synthesis) approaches. Both approaches achieved a very low latency value of 31.25 ns, corresponding to only 15% of the latency budget. HLS provided advantages such as requiring much less design effort, enabling early testing, and having slightly higher performance in terms of timing slack and logic resource usage.