A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Logic-compatible gain-cell embedded DRAM (GC-eDRAM) is an emerging alternative to conventional SRAM for memory-dominated system-on-chip (SoC) designs due to its high-density, low-power, and two-ported operation. Although GCs have a limited data retention time (DRT) at deeply scaled technology nodes, there are many DSP applications which only require short-term data storage and can therefore avoid refresh. In this paper, we present a novel single-well mixed 3T GC implementation in 28 nm FD-SOI technology. The proposed GC is supplied with body-bias control to improve the DRT by suppressing the leakage through the write port, and extend the maximum operating frequency by forward body-biasing the read port. A 24 kbit GC-eDRAM macro implementing the proposed 3T GC was fabricated in 28 nm FD-SOI technology, resulting in the highest density logic-compatible embedded memory fabricated in any 28 nm process with over 2x higher density compared to a 6T SRAM cell, over 4x higher DRT compared to a conventional 3T GC, and 38 x 47 x lower static power compared to conventional single-ported and two-ported SRAMs.

Published in:
2019 Ieee Asian Solid-State Circuits Conference (A-Sscc), 219-222
Presented at:
15th IEEE Asian Solid-State Circuits Conference (A-SSCC), Macao, PEOPLES R CHINA, Nov 04-06, 2019
Jan 01 2019
New York, IEEE

 Record created 2020-10-01, last modified 2020-10-29

Rate this document:

Rate this document:
(Not yet reviewed)