Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, and thermal and power management becomes problematic. In this context, Integrated Flow Cell Array (FCA) technology, which consists of inter-tier microfluidic channels, combines on-chip electrochemical power generation and liquid cooling of 3D MPSoCs. When connected to power delivery networks (PDN) of dies, FCAs provide an additional current compensating voltage drop (IR-drop) across PDNs. In this paper, we evaluate for the first time how IR-drop reduction and liquid cooling capabilities of the FCAs scale with advanced CMOS processes. We develop a framework to quantify the system-level impact of FCAs at different technology nodes, from 22nm to 3nm. Our results show that, across all considered nodes, FCAs reduce the peak temperature of a multi-core processor (MCP) and a Machine Learning (ML) accelerator by over 22°C and 35°C, respectively, compared to off-chip direct liquid cooling. Moreover, the low operation voltages and high temperatures at advanced nodes improve up to 2× FCA power generation. Hence, FCAs allow us to keep the IR-drop below 5% for both the MCP and ML accelerator, saving over 10% TSV-reserved chip area, as opposed to using a High-Performance Computing (HPC) MPSoC liquid cooling solution.

Presented at:
ACM Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, September, 7-9, 2020
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 Record created 2020-06-02, last modified 2020-06-17

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