Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures
Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthreshold slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.
WOS:000520409500025
2019-01-01
978-1-7281-1539-9
New York
Proceedings of the European Solid-State Device Research Conference
98
101
REVIEWED
Event name | Event place | Event date |
Cracow, POLAND | Sep 23-26, 2019 | |