A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed and routed digital signal processor (DSP) following a 10-bit time-interleaved pipelined successive-approximation register analog-to-digital converter (TI-PISAR ADC). The prototype RX chip implemented in a 14-nm FinFET process demonstrates a lane data rate of 56 Gb/s dissipating 161 mW including the ADC and the DSP power. The energy efficiency of 1.2 pJ/b for the DSP and 2.9 pJ/b for the entire RX was achieved with the data-rate of 56 Gb/s for communicating over channels exhibiting up to 28-dB loss at 14 GHz with a bit-error-rate (BER) better than 2e-4.


Published in:
Ieee Journal Of Solid-State Circuits, 55, 1, 38-48
Presented at:
IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, Feb 17-21, 2019
Year:
Jan 01 2020
Publisher:
Piscataway, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN:
0018-9200
1558-173X
Keywords:
Laboratories:




 Record created 2020-03-03, last modified 2020-04-20


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)