High-Performance III-V MOSFETs and Tunnel-FETs Integrated on Silicon

Silicon transistor scaling is approaching its end and a transition to novel materials and device concepts is more than ever essential. High-mobility compound semiconductors are considered promising candidates to replace silicon, targeting low-power logic and high-speed electronics. However, to enable large scale and cost-effective integration, it is crucial to address the challenge of integrating III-V devices on silicon substrates and to ensure CMOS processing compatibility. In this work, possibilities and limitations of III-V-on-silicon electronics are explored experimentally. A material platform, suitable for 3D and co-planar integration of InGaAs-based devices with multiple functionalities and featuring CMOS compatible process modules is here presented. Scaled InGaAs FinFETs showing record high on-current of 350 µA/µm (IOFF = 100 nA/µm and VDD = 0.5 V), for III-V FETs on Si are demonstrated. Comparable device performance is also achieved in a 3D sequential integration fashion, where InGaAs transistor are fabricated on top of a Si CMOS device layer. The designed fabrication flow, targeting high-performance devices, can be adapted to the heterogeneous integration of multiple III-V compounds. Hence, following the same approach, the first sub-thermionic heterojunction InGaAs/GaAsSb Tunnel-FETs on silicon are reported. Tunnel-FETs belong to the category of steep-slope devices and can overcome MOSFET fundamental limitations taking advantage of quantum transport laws. In this work, some of the key technological challenges to fabricate III-V Tunnel-FETs are addressed and their impact on performance is experimentally demonstrated.


Advisor(s):
Ionescu, Mihai Adrian
Moselund, Kirsten Emilie
Year:
2020
Publisher:
Lausanne, EPFL
Keywords:
Laboratories:
NANOLAB


Note: The status of this file is: Anyone


 Record created 2020-01-28, last modified 2020-10-27

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