Parallel FPGA routing: Survey and challenges

As transistor scaling is slowing down [1], other opportunities for ensuring continuous performance increase have to be explored. Field programmable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud [2]. The latter makes them available to everyone in need of the immense computing power and data throughput they can offer. However, one important issue needs to be resolved first - the time to compile an industrial-scale design for an FPGA must be drastically reduced. Researchers have been looking for ways to accelerate FPGA routing through parallelism, since routing is one of the most time-consuming compilation steps. However, the ideal solution has not been found yet. This paper provides a survey of parallel FPGA routers, with the aim to identify their strengths and weaknesses, thus suggesting directions to take in further efforts for acceleration.


Published in:
2017 27th International Conference on Field Programmable Logic and Applications (FPL), 1-8
Presented at:
2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, September 4-8, 2017
Year:
Jan 01 2017
Other identifiers:
Laboratories:




 Record created 2019-10-24, last modified 2019-10-29


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