LUT-Based Hierarchical Reversible Logic Synthesis

We present a synthesis framework to map logic networks into quantum circuits for quantum computing. The synthesis framework is based on lookup-table (urn networks, which play a key role in conventional logic synthesis. Establishing a connection between LUTs in an LUT network and reversible single-target gates in a reversible network allows us to bridge conventional logic synthesis with logic synthesis for quantum computing, despite several fundamental differences. We call our synthesis framework LUT-based hierarchical reversible logic synthesis (LHRS). Input to LHRS is a classical logic network representing an arbitrary Boolean combinational operation; output is a quantum network (realized in terms of Clifford-FT gates). The framework allows one to account for qubit count requirements imposed by the overlying quantum algorithm or target quantum computing hardware. In a fast first step, an initial network is derived that only consists of single-target gates and already completely determines the number of qubits in the final quantum network. Different methods are then used to map each single-target gate into Clifibrd+T gates, while aiming at optimally using available resources. We demonstrate the versatility of our method by conducting a design space exploration using different parameters on a set of large combinational benchmarks. On the same benchmarks, we show that our approach can advance over the state-of-the-art hierarchical reversible logic synthesis algorithms.


Published in:
Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems, 38, 9, 1675-1688
Year:
Sep 01 2019
Publisher:
Piscataway, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN:
0278-0070
1937-4151
Keywords:
Laboratories:




 Record created 2019-09-11, last modified 2020-04-20


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