Developing large arrays of single-photon avalanche diodes (SPADs) with on-chip time-correlated single-photon counting (TCSPC) capabilities continues to be a difficult task due to stringent silicon real estate constraints, high data rates and system complexity. As an alternative to TCSPC, time-gated architectures have been proposed, where the numbers of photons detected within different time gates are used as a replacement to the usual time-resolved luminescence decay. However, because of technological limitations, the minimum gate length implement is on the order of nanoseconds, longer than most fluorophore lifetimes of interest. However, recent FLIM measurements have shown that it is mainly the gate step and rise/fall time, rather than its length, which determine lifetime resolution. In addition, the large number of photons captured by longer gates results in higher SNR. In this paper, we study the effects of using long, overlapping gates on lifetime extraction by phasor analysis, using a recently developed 512×512 time-gated SPAD array. The experiments used Cy3B, Rhodamine 6G and Atto550 dyes as test samples. The gate window length was varied between 11.3 ns and 23 ns while the gate step was varied between 17.86 ps and 3 ns. We validated the results with a standard TCSPC setup and investigated the case of multi-exponential samples through simulations. Results indicate that lifetime extraction is not degraded by the use of longer gates, nor is the ability to resolve multi-exponential decays.