On the Dynamic Performance of Laterally Gated Transistors

Laterally gated transistors have been proposed as an innovative device architecture in which a semiconducting channel is controlled by side gates. In this sense, the gate can either be in contact with the sidewalls or be separated by a gap. In the latter case, the relatively large transconductance together with the small gate capacitance offers a promising potential for future RF devices. The DC performance of these transistors has been studied in the literature; however, there is a lack of investigation on their dynamic performance. Here, we show that the channel control in a laterally gated transistor with gate-channel separation can come from either the gate electric field or the trapped carriers in the surface or bulk. The latter effect results in very slow time responses. We also show that trap states can be more dominant in degrading the dynamic performance of these devices than in planar-gate transistors. The measurement method employed in this letter can be used to determine whether the control is from the gate electric-field or trapped carriers. This letter aims to clarify the related studies in the literature and opens a way to understand and optimize the laterally gated transistors.


Published in:
IEEE Electron Device Letters, 40, 7, 1171-1174
Year:
May 30 2019
Laboratories:




 Record created 2019-07-01, last modified 2019-07-03

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