Toward ultra-low power design methodology for frequency generation in the IoT design space

Today, the semiconductor industry is feeding our digital world with more and more data coming from compact embedded electronics that are monitoring our environment and feeding analytics for action. Interaction with our digital world is mostly achieved through Internet connectivity. The idea of the Internet of Things (IoT) extends the concept of a digital world into the physical world through these autonomous systems on a chip (SoC). In a ubiquitous object with a small-form-factor, power is a significant concern. Device lifetime is a key. The most power-hungry functions, such as wireless radio operation, could be scheduled or made dependent upon other conditions. Most of these objects are battery operated, some harvest energy from their environments, or combine the two modes in case of energy sparsity. SoC should be in low-power mode when sleeping and energy-efficient when active. Once the SoC wakes up, it uses multiple clock sources to drive the processing, the memory, the sensor interface and the wireless connectivity. There are currently no solutions available that would meet all these requirements. Surveys estimate that clocking accounts for one-third of SoC power dissipation. In this context, the objective of this research is to propose design methodologies for frequency generation. As highlighted earlier, the problem is broad, and therefore we review the metrics proposed in the literature and identify the trade-offs and Figures-of-merit (FoM). When addressing the production of circuits operated at a moderate inversion level, the process variability degrades the correlation between silicon and simulation results; the divot corner transistor effect was mitigated and modelled. The proposed design strategy relies on the use of self-biased circuits which benefit from enhanced robustness to process, supply, and temperature variation; this was combined with astute use of inversion level properties as well as merging functions reusing the same transistor. Moreover, the proposed methodology can further extend to other domains such as SoC security with a random number generator leveraging the phase noise, in SoC signal chain fast locking phase-locked loops, and in SoC power chains with a 60mV cold-start function from a thermoelectric generator. This dissertation, case-studies, and results validate the design guidelines from which we manufactured eleven circuits.


Advisor(s):
Kayal, Maher
Krummenacher, François
Year:
2019
Publisher:
Lausanne, EPFL
Keywords:
Laboratories:
GR-KA


Note: The status of this file is: EPFL only


 Record created 2019-04-15, last modified 2019-10-18

Fulltext:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)