A Fast, Reliable and Wide-voltage-range In-memory Computing Architecture

In-Memory Computing (IMC) solutions, and particularly bitline computing in SRAM, appear promising as they mitigate one of the most energy consuming aspects in computation: data movement. In this work we propose a fast (2.4Ghz for bitwise operations and 2.4/1.5Ghz for 32/64bit additions respectively), reliable (no read disturb issues) and wide voltage range (from 0.6 to 1V) 6T SRAM-based IMC architecture using local bitlines and a fast carry adder pitched below the memory subarray. We verify the proposed architecture through layout and variability aware simulations in 28nm bulk high performances technology PDK.


Presented at:
IEEE/ACM Design Automation Conference (DAC), Las Vegas, Nevada, USA., june 2-6, 2019
Year:
Jun 02 2019
Keywords:
Laboratories:




 Record created 2019-04-03, last modified 2019-06-19

Fulltext:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)