Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

This paper discusses the advantages of subthreshold logic for True Random Number Generators (TRNG). In this work, the entropy is modeled, and a lower bound of Shannon's entropy per output bit can quickly be estimated. Thanks to this model, sizing TRNGs in subthreshold logic is quite simple and defining design guidelines for low-energy and low-area TRNGs is straightforward. A TRNG in 180nm CMOS technology has been designed, demonstrating low complexity (305 gates) and energy efficacy (30pJ/bit) at 0.5 Kbit/s.


Published in:
Proceedings 2018 Ieee Symposium In Low-Power And High-Speed Chips (Cool Chips)
Presented at:
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), Yokohama, JAPAN, Apr 18-20, 2018
Year:
Jan 01 2018
Publisher:
New York, IEEE
ISSN:
2473-4683
ISBN:
978-1-5386-6103-1
Keywords:




 Record created 2019-01-23, last modified 2019-12-05


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