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  4. Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator
 
conference paper

Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

Coustans, Mathieu  
•
Cherkaoui, Abdelkarim
•
Fesquet, Laurent
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January 1, 2018
Proceedings 2018 Ieee Symposium In Low-Power And High-Speed Chips (Cool Chips)
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)

This paper discusses the advantages of subthreshold logic for True Random Number Generators (TRNG). In this work, the entropy is modeled, and a lower bound of Shannon's entropy per output bit can quickly be estimated. Thanks to this model, sizing TRNGs in subthreshold logic is quite simple and defining design guidelines for low-energy and low-area TRNGs is straightforward. A TRNG in 180nm CMOS technology has been designed, demonstrating low complexity (305 gates) and energy efficacy (30pJ/bit) at 0.5 Kbit/s.

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Type
conference paper
DOI
10.1109/CoolChips.2018.8373081
Web of Science ID

WOS:000455046600009

Author(s)
Coustans, Mathieu  
Cherkaoui, Abdelkarim
Fesquet, Laurent
Terrier, Christian  
Salgado, Stephanie
Eberhardt, Thomas
Kayal, Maher  
Date Issued

2018-01-01

Publisher

IEEE

Publisher place

New York

Published in
Proceedings 2018 Ieee Symposium In Low-Power And High-Speed Chips (Cool Chips)
ISBN of the book

978-1-5386-6103-1

Series title/Series vol.

Proceedings for IEEE COOL CHIPS

Subjects

Computer Science, Hardware & Architecture

•

Engineering, Electrical & Electronic

•

Computer Science

•

Engineering

•

applied cryptography

•

random numbers generators

•

asynchronous circuits

•

subthreshold logic

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
GR-KA  
Event nameEvent placeEvent date
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)

Yokohama, JAPAN

Apr 18-20, 2018

Available on Infoscience
January 23, 2019
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/153813
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