Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an initial code optimization to improve the memory access bottleneck, SDSoC pragmas have been introduced to boost system performance through an increased parallelism. Preliminary results have shown significant reductions in the execution time and the energy consumption compared to the conventional software implementation.


Published in:
2018 31st IEEE International System-on-Chip Conference (SOCC), 158-162
Presented at:
2018 31st IEEE International System-on-Chip Conference (SOCC), Arlington, Virginia, USA, September 4-7, 2018
Year:
Sep 06 2018
Publisher:
IEEE
ISBN:
978-1-5386-1491-4
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Note: The status of this file is: Anyone


 Record created 2018-09-06, last modified 2020-10-25

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