Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links

The exponential growth of Internet traffic and related demands for higher communication speed pushes processor-to-processor and processor-to-memory interconnects to provide further higher data-rate. Often time, processor-to-memory interconnects’ speed is limited by reflections due to their multi-drop bus (MDB) channel nature, and processor-to-processor interconnects’ speed is limited by inter-symbol interference due to the slowly-decaying channel pulse response and the operating speed and/or power efficiency of the equalization circuits. For the data-rate to continue its exponential growth, more complex modulation and equalization techniques should be employed in the transmitter (TX) and receiver (RX) circuits, given the power and silicon area budget. This thesis presents a signaling scheme designed to overcome equalization challenges related to reflection-limited interfaces such as MDB interfaces. By shaping the spectrum of the transmitted signal appropriately to the channel’s frequency characteristics, the proposed signaling enables minimization of energy-loss due to reflections. While the data-rate of conventional non-return-to-zero (NRZ) signaling over MDB is limited by its first notch frequency unless power-hungry decision-feedback equalizer (DFE) is employed, the proposed signaling scheme allows overcoming such limitation by simple encoding and decoding. Analogmulti-tone (AMT) signaling with single-sideband (SSB) radio-frequency (RF)-bands for efficient bandwidth usage is proposed for lossy point-to-point interfaces. The mutually orthogonal RF sub-bands feature self-equalization throughout the propagation through the communication medium and down-conversion at the RX, without necessitating the presence of conventional equalizers. To enable communication with higher modulation order for more efficient bandwidth utilization, an analog-to-digital converter (ADC)-based discrete multi-tone (DMT) RX is designed and implemented. Thanks to the high bandwidth efficiency of approximately 5.33 bits/Hz (including the cyclic prefix of DMT symbol) using 64-level quadrature amplitude modulation (64-QAM), the implemented RX undergoes less channel attenuation as compared to its 4-level pulse amplitude modulation (PAM-4) counterpart given target communication speed through the same channel. Moreover, the inherently parallel RX architecture of DMT signaling allows the RX digital signal processing (DSP) elements to be designed in semi-custom style without stringent timing constraints. Finally, a PAM-4 RX based on ADC with fully-digital equalization is presented. With register-transfer level (RTL) modeling of the designed digital equalizer, the results demonstrate the feasibility of frequency-domain equalization of the time-domain signal using Fourier transform and its inversion. The proposed frequency-domain equalization technique removes the necessity of symbol-by-symbol feedback loop in DSP that is present in DFE, relaxing critical timing constraints in DSP synthesis.


Advisor(s):
Leblebici, Yusuf
Year:
2018
Publisher:
Lausanne, EPFL
Keywords:
Laboratories:
LSM


Note: The status of this file is: EPFL only


 Record created 2018-07-27, last modified 2018-10-22

Fulltext:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)