End-to-End Industrial Study of Retiming

Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic without changing the functionality. Despite significant efforts spent on sequential optimization since 1980's, there are few works discussed its performance in an end to-end design flow. The retiming algorithms were mostly evaluated at the logic level. However, it turns out that the retiming results at logic level could be significantly different than evaluating the physical level.
This paper provides the findings of how retiming algorithms perform in an end-to-end industrial design flow, with seven industry designs taken from a recent 14nm microprocessor. Experiments are conducted with several complete industrial design flows. The evaluations are made at the end of the physical design flow. The experimental results show that the performance (design quality) of the retiming algorithms vary on the designs. Based these experimental results, we discover a feature that describes the retiming potentials of sequential designs. This model successfully forecast whether the given industrial designs could be significantly improved by retiming in an end-to-end design flow, regarding timing, area, and power.


Published in:
IEEE Computer Society Annual Symposium on VLSI, 203-208
Presented at:
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'18), Hong Kong SAR, China, July 9-11, 2018
Year:
Jul 11 2018
Publisher:
IEEE
ISSN:
2159-3469
2159-3477
Keywords:
Note:
ERC Cybercare 669354 / IBM Watson Research Center
Laboratories:




 Record created 2018-06-08, last modified 2019-03-17

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