Conventional input/output (IO) links consume power, independent of changes
in the bandwidth demand by the system they are deployed in. As the system is
designed to satisfy the peak bandwidth demand, most of the time the IO links
are idle but still consuming power. In big data centers, the overall utilization
ratio of IO links is less than 10%, corresponding to a large amount of energy
wasted for idle operation.
This work demonstrates a 60 Gb/s high sensitivity non-return-to-zero (NRZ)
optical receiver in 14 nm FinFET technology with less than 7 ns power-on time.
The power on time includes the data detection, analog bias settling, photo-diode
DC current cancellation, and phase locking by the clock and data recovery circuit
(CDR). The receiver autonomously detects the data demand on the link
via a proposed link protocol and does not require any external enable or disable
signals. The proposed link protocol is designed to minimize the off-state power
consumption and power-on time of the link.
In order to achieve high data-rate and high-sensitivity while maintaining
the power budget, a 1-tap decision feedback equalization method is applied in
digital domain. The sensitivity is measured to be -8 dBm, -11 dBm, and -13 dBm
OMA (optical modulation amplitude) at 60 Gb/s, 48 Gb/s, and 32 Gb/s data rates,
respectively. The energy efficiency in always-on mode is around 2.2 pJ/bit for all
data-rates with the help of supply and bias scaling.
The receiver incorporates a phase interpolator based clock-and-data recovery
circuit with approximately 80 MHz jitter-tolerance corner frequency, thanks to
the low-latency full custom CDR logic design.
This work demonstrates the fastest ever reported CMOS optical receiver and
runs almost at twice the data-rate of the state-of-the-art CMOS optical receiver
by the time of the publication. The data-rate is comparable to BiCMOS optical
receivers but at a fraction of the power consumption.