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  4. High-level system synthesis and optimization of dataflow programs for MPSoCs
 
conference paper

High-level system synthesis and optimization of dataflow programs for MPSoCs

Bezati, E.
•
Brunet, S. Casale
•
Mattavelli, M.
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November 6, 2016
2016 50th Asilomar Conference on Signals, Systems and Computers

The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on reconfigurable and embedded devices. Past research has shown that raising the level of abstraction of design stages does not necessarily gives penalties in terms of performance or resources. Dataflow programs provide behavioral descriptions capable of expressing both sequential and parallel algorithms and enable natural design abstractions, modularity, and portability. In this paper, a tool implementing dataflow programs onto embedded heterogeneous platforms by means of high-level synthesis, software synthesis and interface synthesis is presented for MPSoCs platfroms.

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Type
conference paper
DOI
10.1109/ACSSC.2016.7869072
Author(s)
Bezati, E.
Brunet, S. Casale
Mattavelli, M.
Janneck, J. W.
Date Issued

2016-11-06

Published in
2016 50th Asilomar Conference on Signals, Systems and Computers
Start page

417

End page

421

Subjects

Computer architecture

•

Software

•

Complexity theory

•

Hardware

•

Optimization

•

Parallel processing

•

Hardware design languages

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
SCI-STI-MM  
Available on Infoscience
March 13, 2018
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/145504
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