Notice détaillée
Titre
Kim, Gain
Sciper ID
195141
Laboratoires affiliés
LSM
Publications
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET
A Study on the Programming Structures for RRAM-based FPGA Architectures
A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links
Analysis, Optimization, and Modeling of Analog Multi-Tone Serial Data Transceivers
Architectural Modeling of a Single-Sideband Wireline Serial Data Transceiver for Multi-Drop I/O
Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme
Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion
Voir toutes les publications (17)
A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET
A Study on the Programming Structures for RRAM-based FPGA Architectures
A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links
Analysis, Optimization, and Modeling of Analog Multi-Tone Serial Data Transceivers
Architectural Modeling of a Single-Sideband Wireline Serial Data Transceiver for Multi-Drop I/O
Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme
Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion
Voir toutes les publications (17)
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